A 0.4 V, 12.2 pW Leakage, 36.5 fJ/Step Switching Efficiency Data Retention Flip-Flop in 22 nm FDSOI

Funding Number

62350610271

Funding Sponsor

National Natural Science Foundation of China

Find in your Library

https://doi.org/10.1109/TVLSI.2024.3453946

All Authors

Yuxin Ji, Yuhang Zhang, Changyan Chen, Jian Zhao, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li

Document Type

Research Article

Publication Title

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Date

1-1-2024

doi

10.1109/TVLSI.2024.3453946

Abstract

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW, 1.4 × -3.8 × less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step, 1.2 × -4 × less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

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