Abstract

The globalization of the semiconductor supply chain has introduced critical vulnerabilities, including intellectual property (IP) piracy, reverse engineering, and hardware tampering. While traditional logic locking offers a baseline of defense, the emergence of powerful Boolean satisfiability (SAT) solvers has rendered many static obfuscation techniques ineffective. This work proposes a Dynamic Multi- Layered Hardware Obfuscation Framework that utilizes Behavioral Drift Locking (BDL) to provide a robust defense-in-depth against advanced adversarial models. The methodology integrates four synergistic layers: • Dynamic Key Management using a time-dependent rotation mechanism that updates keys every clock cycle to prevent static analysis. • Control Obfuscation through opcode masking. • Data Obfuscation using striped key segments and BDL • Integrity Verification via dual-rail anti-SAT logic and redundant consistency checks. Unlike traditional static approaches, the BDL mechanism ensures that circuit behavior periodically drifts into erroneous states unless re-synchronized with a secret internal condition, effectively removing the single point of failure associated with static key leakage. The framework was implemented in Verilog and validated on ALU, FFT, and AES cores using Intel Quartus Prime and ModelSim. Security evaluations using CryptoMiniSat and AppSAT demonstrate high resilience, with solvers failing to recover the key after 1,000,000 iterations. Experimental results quantify the design overhead, showing a maximum area increase of 8.76% and a power overhead of 9.00% for the most aggressively locked ALU core, while maintaining high performance with a critical path delay impact of only 7.50%. These results prove that a light, layered approach can achieve strong SAT-resistance and side-channel resilience with practical overheads suitable for modern processors and cryptographic modules

School

School of Sciences and Engineering

Department

Electronics & Communications Engineering Department

Degree Name

MS in Electronics & Communication Engineering

Graduation Date

Fall 2-14-2026

Submission Date

1-25-2026

First Advisor

Dr.Yehea Ismail

Committee Member 1

Dr.Yehea Ismail

Committee Member 2

Dr.Hassanein Amer

Committee Member 3

Dr.Mohamed Saleh

Extent

53 p.

Document Type

Master's Thesis

Institutional Review Board (IRB) Approval

Approval has been obtained for this item

Disclosure of AI Use

Thesis editing and/or reviewing

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