Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment

Author

Ahmed MohamedFollow

Abstract

This work aims at providing a concise automated flow to predict the effect of Single Event Transients (SETs) on ASIC chips by developing a method to characterize the circuit susceptibility to SET pulses propagation and then generation of the required input vectors that sensitize the victim paths. A new enhanced method for SET electrical propagation modeling is proposed and compared to a previously published analytical model. The method was applied on different standard cells libraries built over XFAB Xh018 technology and verified for accuracy against simulations. The new method showed enhancement in accuracy compared with previous work in literature. Industrial ATPG tool for SET test vectors generation was used with some modifications to its native flow to fit the different nature of SETs. The proposed steps were tested using ISCAS ’85 benchmarks synthesized with the XFAB standard cells.

School

School of Sciences and Engineering

Department

Electronics & Communications Engineering Department

Degree Name

MS in Electronics & Communication Engineering

Graduation Date

Spring 5-25-2021

Submission Date

5-25-2021

First Advisor

Ahmed Abou-Auf

Committee Member 1

Amr Wassal

Committee Member 2

Mohab Anis

Extent

76p.

Document Type

Master's Thesis

Institutional Review Board (IRB) Approval

Not necessary for this item

Recommended Citation

APA Citation

Mohamed, A. (2021).Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment [Master's Thesis, the American University in Cairo]. AUC Knowledge Fountain.
https://fount.aucegypt.edu/etds/1645

MLA Citation

Mohamed, Ahmed. Fault Modeling and Test Vector Generation for ASIC Devices Exposed to Space Single Event Environment. 2021. American University in Cairo, Master's Thesis. AUC Knowledge Fountain.
https://fount.aucegypt.edu/etds/1645