Cyclic memory: a low-latency, single-buffer technique for FMCW LiDAR interleaving/de-interleaving

Fifth Author's Department

Computer Science & Engineering Department

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https://doi.org/10.1007/s10470-025-02476-z

All Authors

O. S. Hafez O. A. Abouelfetouh Y. O. Mohamed M. N. Hasaneen R. A. Elomda O. H. Fathy Y. H. Hassan M. M. Mahroos M. M. Ghouneem

Document Type

Research Article

Publication Title

Analog Integrated Circuits and Signal Processing

Publication Date

9-1-2025

doi

10.1007/s10470-025-02476-z

Abstract

Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a critical constraint: the system must collect new data block while simultaneously reorganizing previously acquired data block–all without interrupting pipeline throughput. A ping-pong buffer allows a system to do so by doubling buffering memory size. This idea increases memory data throughput by not halting the pipeline operation. This paper presents a memory read/write algorithm called “Cyclic Memory” as an alternative to the ping-pong buffering algorithm for the data interleaving/de-interleaving process. Unlike the ping-pong buffering algorithm, the cyclic memory algorithm does not require double buffering. This means that cyclic memory cuts memory requirements in half, uses less area, and consumes less power. This paper will discuss the derivation of the algorithm as well as its implementation.

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