An Ultra Low Voltage Energy Efficient Level Shifter with Current Limiter and Improved Split-Controlled Inverter

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https://doi.org/10.1109/TCSII.2024.3379448

All Authors

Chao Wang, Yang Wei Lim, Yuxin Ji, Jiajie Huang, Wangzilu Lu, Fakhrul Zaman Rokhani, Yehea Ismail, Yongfu Li

Document Type

Research Article

Publication Title

IEEE Transactions on Circuits and Systems II: Express Briefs

Publication Date

5-1-2024

doi

10.1109/TCSII.2024.3379448

Abstract

This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum V_DDL of 100 mV at V_DDH= 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 - 1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications.

First Page

2569

Last Page

2573

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