UVM Based Verification Framework for Deep Learning Hardware Accelerator: Case Study

Author's Department

Electronics & Communications Engineering Department

Fourth Author's Department

Electronics & Communications Engineering Department

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https://doi.org/10.1109/ICECET61485.2024.10698126

All Authors

Randa Aboudeif, Tasneem A. Awaad, Mohamed Abdelsalam, Yehea Ismail

Document Type

Research Article

Publication Title

International Conference on Electrical, Computer, and Energy Technologies, ICECET 2024

Publication Date

1-1-2024

doi

10.1109/ICECET61485.2024.10698126

Abstract

Hardware Verification of Deep Learning Accelerators (DLAs) has become critically important for testing the reliability and trustworthiness of Learning Enabled Autonomous Systems (LEAS). In this paper, we introduce a scalable, reusable, and efficient hardware verification framework for DLAs using the Universal verification methodology (UVM). The verification environment is focused on testing the inference functionality of the perception module in LEAS for different DLA designs. Moreover, the verification environment is portable across simulation and hardware-assisted verification platforms for emulation and FPGA prototyping. To assess our proposed UVM design methodology, we have applied it to the Nvidia Deep Learning Accelerator (NVDLA), an open-source core for DLAs as a case study.

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Conference Paper. Record derived from SCOPUS.

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