Fast and Accurate Machine Learning Compact Models for Interconnect Parasitic Capacitances Considering Systematic Process Variations

Author's Department

Electronics & Communications Engineering Department

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https://doi.org/10.1109/ACCESS.2022.3142330

All Authors

MOHAMED SALEH ABOUELYAZID, SHERIF HAMMOUDA, AND YEHEA ISMAIL

Document Type

Research Article

Publication Title

IEEE Access

Publication Date

1-6-2022

doi

10.1109/ACCESS.2022.3142330

Abstract

A novel modeling methodology is developed for interconnect parasitic capacitances in rule-based extraction tools. Traditional rule-based extraction tools rely on pattern matching operations to match every interconnect structure with corresponding pre-characterized capacitance formulas. Such a method suffers from three main problems including limited pattern coverages, potential pattern mismatches, and limited handling of systematic process variations. These problems prohibit rule-based methods from coping with the new capacitance extraction accuracy requirements in advanced process nodes. The proposed methodology overcomes these problems by providing machine learning compact models for interconnect parasitic capacitances that cover varieties of realistic cross-section metal patterns. Those models efficiently include the impact of systematic process variations on parasitic capacitances. Moreover, each model can handle thousands of patterns replacing thousands of existing capacitance formulas. The input to the models is a cross-section pattern that is represented by a novel vertex-based pattern representation. The models are implemented using two different machine learning methods: neural networks and support vector regressions. The two methods are tested and compared to each other. The proposed methodology is tested over thirteen test chips of 28nm, 14nm, and 7nm process nodes with more than 6.7M interconnect cross-section patterns. The results show that the proposed methodology provided outstanding accuracy as compared to field-solvers and rule-based models with an average error < 0.15% and a standard deviation < 3.3%, whereas the average errors and standard deviations of rule-based models exceed 6%, for the same test chips. Also, the computational runtimes of the compact models are almost 2.5X faster than rule-based models.

First Page

7533

Last Page

7553

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