Author's Department

Electronics & Communications Engineering Department

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https://doi.org/10.1109/access.2022.3203077

All Authors

MOHAMED SALEH ABOUELYAZID, SHERIF HAMMOUDA, AND YEHEA ISMAIL

Document Type

Research Article

Publication Title

IEEE Access

Publication Date

8-31-2022

doi

10.1109/access.2022.3203077

Abstract

A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed based on an incremental parasitic extraction and a fast optimization methodology. Existing routing optimization methodologies rely on many circuit simulations, detailed sensitivity analysis, and inefficient simple parasitic models to optimize routes. Moreover, they do not provide a mechanism to help layout designers in identifying problematic layout geometries that have a bad impact on a route’s performance. The proposed methodology works on overcoming such problems by providing three features. First, it provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route’s performance to corresponding layout geometries very fast. Therefore, they can correlate the problems of a route’s performance to specific layout geometries. Second, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Third, the proposed methodology uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently. The incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy. The proposed methodology is tested over different designs of 7nm and 65nm process nodes. The results show that the proposed methodology managed to identify and optimize the problematic geometries in critical routes efficiently with up to 10% performance improvements and a speedup of 3 to 9X as compared to traditional template-based methods.

First Page

92740

Last Page

92759

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