Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Author's Department

Electronics & Communications Engineering Department

Second Author's Department

Electronics & Communications Engineering Department

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https://www.worldscientific.com/doi/10.1142/S0218126618500561

All Authors

Osama Abdelkader; Mohamed Mohie El-Din; Hassan Mostafa; Hamdy Abdelhamid; Hossam A. H. Fahmy; Yehea Ismail; Ahmed M. Soliman

Document Type

Research Article

Publication Title

Journal of Circuits, Systems and Computers

Publication Date

1-1-2018

doi

10.1142/S0218126618500561

Abstract

The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20nm down to 7nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circuits: 2-bit adder, 4-bit NAND and cascaded flip-flops chain. The study shows that power, delay and PDP of the FPGA cluster are improved as we scale down the technology. An example for improvement is that for 7nm 2-bit adder, circuit speed is 15% higher than its value at 20nm and PDP at 7nm is reduced by 43% compared to its value at 20nm. The impacts of temperature and threshold voltage variations on FPGA cluster performance are also reported after evaluating a 2-bit adder circuit as a benchmark which is then used to calculate the design constraints to meet 99.9% yield percentage.

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