Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison

Second Author's Department

Computer Science & Engineering Department

Find in your Library

https://doi.org/10.1109/MWSCAS47672.2021.9531753

Document Type

Research Article

Publication Title

Midwest Symposium on Circuits and Systems

Publication Date

8-9-2021

doi

10.1109/MWSCAS47672.2021.9531753

Abstract

Computer Aided Design (CAD) tools are widely used in Application Specific Integrated Circuit (ASIC) design. CAD tools provide a simple process for the IC design. For that purpose open source EDA tools are used for study and research of an IC design. This describes how the open source EDA tools could help the researchers and students to learn and fabricate their own Integrated circuits. In this paper, we present the digital ASIC implementation of RISC-V "DwarfRV32". The design is implemented using two approaches, which are the OpenLane flow and the Commercial tools. We then compare between the two flows on important parameters like timing performance and power consumption.

First Page

498

Last Page

502

This document is currently not available here.

Share

COinS