Layout regularity metric as a fast indicator of high variability circuits

Author's Department

Electronics & Communications Engineering Department

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https://doi.org/10.1109/SOCC.2013.6749658

Document Type

Research Article

Publication Title

International System on Chip Conference

Publication Date

1-1-2013

doi

10.1109/SOCC.2013.6749658

First Page

43

Last Page

48

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