Litho-friendly decomposition method for self-aligned triple patterning

Author's Department

Electronics & Communications Engineering Department

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https://doi.org/10.1109/TVLSI.2013.2265309

Document Type

Research Article

Publication Title

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Date

1-1-2014

doi

10.1109/TVLSI.2013.2265309

Abstract

Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligned triple patterning (SATP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, the major SATP litho-friendliness requirements are explained. In-silico experiments on SATP process indicate that layout features printed by the structural spacers are the most accurate ones. Therefore, we propose an ILP-based decomposition which avoids decomposition conflicts and maximizes the use of structural spacers simultaneously. Experiments reveal that the proposed method improves overlay robustness and line-edge roughness of the attempted test cases. © 1993-2012 IEEE.

First Page

1170

Last Page

1174

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