Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Authors

Omnia S. Fadl, Cairo University, Faculty of Engineering
Mohamed F. Abu-Elyazeed, Cairo University, Faculty of Engineering
Mohamed B. Abdelhalim, Arab Academy for Science, Technology and Maritime Transport
Hassanein H. Amer, American University in CairoFollow
Ahmed H. Madian, National Center of Radiation Research and Technology, Cairo

Author's Department

Electronics & Communications Engineering Department

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Document Type

Research Article

Publication Title

Journal of Advanced Research

Publication Date

1-1-2016

doi

10.1016/j.jare.2015.02.006

First Page

89

Last Page

94

Recommended Citation

APA Citation

Fadl, O. Abu-Elyazeed, M. Abdelhalim, M. Amer, H. & Madian, A. (2016). Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model. Journal of Advanced Research, 7(1), 89–94. 10.1016/j.jare.2015.02.006
https://fount.aucegypt.edu/faculty_journal_articles/1625

MLA Citation

Fadl, Omnia S., et al. "Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model." Journal of Advanced Research, vol. 7,no. 1, 2016, pp. 89–94.
https://fount.aucegypt.edu/faculty_journal_articles/1625