Synthesizable delay line architectures for digitally controlled voltage regulators
Files
Department
Electronics & Communications Engineering Department
Description
[abstract not available]
Publication Date
12-1-2012
Document Type
Book Chapter
Book Title
International System on Chip Conference
ISBN
SCOPUS_ID:84872572665
Publisher
IEEE
City
Niagara Falls, NY, USA
First Page
72
Last Page
77
Recommended Citation
APA Citation
Haridy, O.
Krishnamurthy, H.
Helmy, A.
&
Ismail, Y.
(2012).Synthesizable delay line architectures for digitally controlled voltage regulators. IEEE. , 72-77
https://fount.aucegypt.edu/faculty_book_chapters/624
MLA Citation
Haridy, Omar, et al.
Synthesizable delay line architectures for digitally controlled voltage regulators. IEEE, 2012.pp. 72-77
https://fount.aucegypt.edu/faculty_book_chapters/624