
Synthesizable delay line architectures for digitally controlled voltage regulators
Files
Department
Electronics & Communications Engineering Department
Abstract
[abstract not available]
Publication Date
12-1-2012
Document Type
Book Chapter
Book Title
International System on Chip Conference
ISBN
SCOPUS_ID:84872572665
Publisher
IEEE
City
Niagara Falls, NY, USA
First Page
72
Last Page
77
Recommended Citation
APA Citation
Haridy, O.
Krishnamurthy, H.
Helmy, A.
&
Ismail, Y.
(2012). Synthesizable delay line architectures for digitally controlled voltage regulators. International System on Chip Conference (pp. 72-77). IEEE.
MLA Citation
Haridy, Omar, et al.
"Synthesizable delay line architectures for digitally controlled voltage regulators." International System on Chip Conference, IEEE, 2012. pp. 72-77