D2. testing of 1.5 bit per stage pipelined analog to digital converter: 5 bits case study

Authors

Sahar M. Hamed, Cairo University, Faculty of Engineering
Ahmed H. Khalil, Cairo University, Faculty of Engineering
M. B. Abdelhalim, Arab Academy for Science, Technology and Maritime Transport
Hassanein H. Amer, American University in CairoFollow
Ahmed H. Madian, National Center of Radiation Research and Technology, Cairo

Files

Department

Electronics & Communications Engineering Department

Abstract

[abstract not available]

Publication Date

1-1-2013

Document Type

Book Chapter

Book Title

National Radio Science Conference, NRSC, Proceedings

ISBN

SCOPUS_ID:84982735892

Publisher

IEEE

City

Cairo, Egypt

First Page

439

Last Page

447

Keywords

1.5 bit/stage, Catastrophic faults, PADC, Structural testing

Recommended Citation

APA Citation

Hamed, S. Khalil, A. Abdelhalim, M. Amer, H. & Madian, A. (2013).D2. testing of 1.5 bit per stage pipelined analog to digital converter: 5 bits case study. IEEE. , 439-447
https://fount.aucegypt.edu/faculty_book_chapters/610

MLA Citation

Hamed, Sahar M., et al. D2. testing of 1.5 bit per stage pipelined analog to digital converter: 5 bits case study. IEEE, 2013.pp. 439-447
https://fount.aucegypt.edu/faculty_book_chapters/610