Testing of memristor ratioed logic (MRL) XOR gate

Authors

A. S. Emara, American University in Cairo
A. H. Madian, Atomic Energy Authority of Egypt
Hassanein H. Amer, American University in CairoFollow
S. H. Amer, American University in Cairo
M. B. Abdelhalim, Arab Academy for Science, Technology and Maritime Transport

Files

Department

Electronics & Communications Engineering Department

Abstract

[abstract not available]

Publication Date

7-2-2016

Document Type

Book Chapter

Book Title

Proceedings of the International Conference on Microelectronics, ICM

ISBN

SCOPUS_ID:85014893425

Publisher

IEEE

City

Giza, Egypt

First Page

181

Last Page

184

Keywords

fault coverage, fault model, Memristors, MRL, production testing, XOR

Recommended Citation

APA Citation

Emara, A. Madian, A. Amer, H. H. Amer, S. & Abdelhalim, M. (2016).Testing of memristor ratioed logic (MRL) XOR gate. IEEE. , 181-184
https://fount.aucegypt.edu/faculty_book_chapters/329

MLA Citation

Emara, A. S., et al. Testing of memristor ratioed logic (MRL) XOR gate. IEEE, 2016.pp. 181-184
https://fount.aucegypt.edu/faculty_book_chapters/329