Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies.


Electronics & Communications Engineering Department

Degree Name

MS in Electronics & Communication Engineering

Graduation Date


Submission Date

July 2012

First Advisor

Ismail, Yehea

Second Advisor

Helmy, Amr



Document Type

Master's Thesis

Library of Congress Subject Heading 1

Voltage regulators.

Library of Congress Subject Heading 2



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Institutional Review Board (IRB) Approval

Not necessary for this item