Negative capacitance circuits for process variations compensation and timing yield improvement
Files
Department
Electronics & Communications Engineering Department
Description
[abstract not available]
Publication Date
1-1-2013
Document Type
Book Chapter
Book Title
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
ISBN
SCOPUS_ID:84901441606
Publisher
IEEE
City
Abu Dhabi, United Arab Emirates
First Page
277
Last Page
280
Keywords
deep sub-micron, Domino logic circuits, negative capacitance circuit, process variations, register file, Timing yield improvement
Recommended Citation
APA Citation
Mostafa, H.
Anis, M.
&
Elmasry, M.
(2013).Negative capacitance circuits for process variations compensation and timing yield improvement. IEEE. , 277-280
https://fount.aucegypt.edu/faculty_book_chapters/604
MLA Citation
Mostafa, Hassan, et al.
Negative capacitance circuits for process variations compensation and timing yield improvement. IEEE, 2013.pp. 277-280
https://fount.aucegypt.edu/faculty_book_chapters/604