Negative capacitance circuits for process variations compensation and timing yield improvement

Authors

Hassan Mostafa, Cairo University
Mohab Anis, American University in CairoFollow
Mohamed Elmasry, University of Waterloo

Files

Department

Electronics & Communications Engineering Department

Abstract

[abstract not available]

Publication Date

1-1-2013

Document Type

Book Chapter

Book Title

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

ISBN

SCOPUS_ID:84901441606

Publisher

IEEE

City

Abu Dhabi, United Arab Emirates

First Page

277

Last Page

280

Keywords

deep sub-micron, Domino logic circuits, negative capacitance circuit, process variations, register file, Timing yield improvement

Recommended Citation

APA Citation

Mostafa, H. Anis, M. & Elmasry, M. (2013). Negative capacitance circuits for process variations compensation and timing yield improvement. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 277-280). IEEE.

MLA Citation

Mostafa, Hassan, et al. "Negative capacitance circuits for process variations compensation and timing yield improvement." Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, IEEE, 2013. pp. 277-280