Analysis and optimization for dynamic read stability in 28nm SRAM bitcells

Authors

Ahmed T. Elthakeb, American University in Cairo
Thomas Haine, Université Catholique de Louvain
Denis Flandre, Université Catholique de Louvain
Yehea Ismail, American University in CairoFollow
Hamdy Abd Elhamid, American University in Cairo

Files

Department

Electronics & Communications Engineering Department

Abstract

[abstract not available]

Publication Date

1-1-2015

Document Type

Book Chapter

Book Title

Proceedings - IEEE International Symposium on Circuits and Systems

ISBN

SCOPUS_ID:84946202553

Publisher

IEEE

City

Lisbon, Portugal

First Page

1414

Last Page

1417

Keywords

6T SRAM, Cell sizing, Dynamic behavior, FD SOI, parasitic capacitances, Read Noise Margin

Recommended Citation

APA Citation

Elthakeb, A. Haine, T. Flandre, D. Ismail, Y. & Elhamid, H. (2015).Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. IEEE. , 1414-1417
https://fount.aucegypt.edu/faculty_book_chapters/451

MLA Citation

Elthakeb, Ahmed T., et al. Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. IEEE, 2015.pp. 1414-1417
https://fount.aucegypt.edu/faculty_book_chapters/451