A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme

Chapter Title

A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme

Files

Department

Electronics & Communications Engineering Department

Description

[abstract not available]

Publication Date

12-9-2015

Document Type

Book Chapter

Book Title

5th International Conference on Energy Aware Computing Systems and Applications, ICEAC 2015

ISBN

SCOPUS_ID:84963612301

Publisher

IEEE

City

Cairo, Egypt

First Page

25

Last Page

28

Keywords

3-level signaling, High speed serial links, on-chip interconnects, SerDes, serial communication on-chip

A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme

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