A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme
Files
Department
Electronics & Communications Engineering Department
Abstract
[abstract not available]
Publication Date
12-9-2015
Document Type
Book Chapter
Book Title
5th International Conference on Energy Aware Computing Systems and Applications, ICEAC 2015
ISBN
SCOPUS_ID:84963612301
Publisher
IEEE
City
Cairo, Egypt
First Page
25
Last Page
28
Keywords
3-level signaling, High speed serial links, on-chip interconnects, SerDes, serial communication on-chip
Recommended Citation
APA Citation
Tadros, R.
Ahmed, A.
Ghoneima, M.
&
Ismail, Y.
(2015).A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. IEEE. , 25-28
https://fount.aucegypt.edu/faculty_book_chapters/395
MLA Citation
Tadros, Ramy N., et al.
A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. IEEE, 2015.pp. 25-28
https://fount.aucegypt.edu/faculty_book_chapters/395