Electronics & Communications Engineering Department
Description or Abstract
The project is to design a 4-bit digital adder, while taking care of performance parameters: area, speed and power consumption, the team has chosen to design according to the cost function: Area*Delay*Power. The project is implemented in three phases: research phase, simulation phase, and evaluation/re-evaluation phase. The adder circuit implemented as Ripple-Carry Adder (RCA), the team added improvements to overcome the disadvantages of the RCA architecture, for instance the first 1-bit adder is a Half Adder, which is faster and more power-efficient, the team was also carefully choosing the gates to match the stated cost function. Gates are implemented using different logic families, according to each gate usage and functionality in the circuit in order to achieve the desired performance. Transistor sizes are also selected based upon simulation and optimization, to reach the needed performance according to the specified cost function. The team was able to reach a 4-bit ripple carry adder that has delay of 1.22 ns with 0.6 uW power consumption (measured at 10 MHz), with 109 transistors. In the re-evaluation phase, the team was able to further improve this to reach 0.99 ns delay with 0.25 uW power consumption (10 MHz) with 97 transistors only.
4-Bit Adder, VLSI design, Ripple-Carry Adder, Simulation
Atwa, Amin; Samir, Ahmed; and Soliman, Fady, "4-Bit Adder Design and Simulation" (2011). Papers, Posters, and Presentations. 11.