Chip multiprocessor (CMP) is replacing the superscalar processor due to its huge performance gains in terms of processor speed, scalability, power consumption and economical design. Since the CMP consists of multiple processor cores on a single chip usually with share cache resources, process synchronization is an important issue that needs to be dealt with. Synchronization is usually done by the operating system in case of shared memory multiprocessors (SMP). This work studies the effect of performing synchronization by the hardware through its integration with the cache coherence protocol. A novel cache coherence protocol, called Lock-based Cache Coherence Protocol (LCCP) was designed and its performance was compared with MESI cache coherence protocol. Experiments were performed by a functional multiprocessor simulator, MP_Simplesim, that was modified to do this work. A novel interconnection network was also designed and tested in terms of performance against the traditional bus approach by means of simulation.
Computer Science & Engineering Department
MS in Computer Science
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(2006).Lock-Based cache coherence protocol for chip multiprocessors [Master’s thesis, the American University in Cairo]. AUC Knowledge Fountain.
Ismail, Ihab. Lock-Based cache coherence protocol for chip multiprocessors. 2006. American University in Cairo, Master's thesis. AUC Knowledge Fountain.