In this thesis we tackle one of the most important fields of research, which is reducing power consumption in digital systems. The importance of this field comes from the fact that nowadays, several digital devices are intensively used in our daily life. Thus, minimizing their power consumption is a common demand from the technological as well as the economical point of view. Some basic definitions in the low power design field are introduced. Besides, a preview of different efforts that were exerted in the field of reducing power consumption of digital systems at various levels of abstraction is presented. A well-known algorithm for the optimization of multiple-level combinational logic networks is described in details. Then, some modifications to the algorithm are proposed to provide the optimization process with the ability to work under delay constraints.

Based on the above algorithm, we introduce a tool that is developed for optimizing power consumption of multiple-level combinational logic networks under delay constraints. The well-known tool for logic-level simulation (ORCAD 9.2®) is used during the experimentation phase to verify the results reported by our tool.


School of Sciences and Engineering


Computer Science & Engineering Department

Degree Name

MS in Computer Science

Date of Award


Online Submission Date


First Advisor

Muhammed Mudawwar

Committee Member 1

Awad Khalil

Committee Member 2

Mohy Mahmoud

Committee Member 3

Hammam El Abd

Document Type



160 leaves

Library of Congress Subject Heading 1

Low voltage integrated circuits.


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Call Number

Thesis 2003/42