Title

Tiling as a loop parallelization technique

Author

Hoda Ahmed Khalil

Department

Computer Science & Engineering Department

Degree Name

MS in Computer Science

Date of Award

6-1-2000

Online Submission Date

January 2000

Document Type

Thesis

Extent

xii, 189 leaves :

Library of Congress Subject Heading 1

Tiling (Mathematics)

Library of Congress Subject Heading 2

Parallel computer.

Rights

The author retains all rights with regard to copyright. The author certifies that written permission from the owner(s) of third-party copyrighted matter included in the thesis, dissertation, paper, or record of study has been obtained. The author further certifies that IRB approval has been obtained for this thesis, or that IRB approval is not necessary for this thesis. Insofar as this thesis, dissertation, paper, or record of study is an educational record as defined in the Family Educational Rights and Privacy Act (FERPA) (20 USC 1232g), the author has granted consent to disclosure of it to anyone who requests a copy.

Recommended Citation

APA Citation

Khalil, H. (2000).Tiling as a loop parallelization technique [Thesis, the American University in Cairo]. AUC Knowledge Fountain.
https://fount.aucegypt.edu/retro_etds/1464

MLA Citation

Khalil, Hoda Ahmed. Tiling as a loop parallelization technique. 2000. American University in Cairo, Thesis. AUC Knowledge Fountain.
https://fount.aucegypt.edu/retro_etds/1464

Call Number

Thesis 2000/51

Location

mgfth