Two-dimensional model for double-gate LDMOSFET devices

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Electronics & Communications Engineering Department

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Mohamed M. El-Dakroury; Zaki Nosseir; Yehea I. Ismail; Hamdy Abdelhamid

Document Type

Research Article

Publication Title

Journal of Computational Electronics

Publication Date





A two-dimensional compact model of a double-gate LDMOSFET is presented in this work. The impact of controlling the drift region resistance by controlling the bias and/or gate metal work function of a separately added second gate of the LDMOSFET electrostatics is investigated while trading off the breakdown behavior in terms of the surface longitudinal field. Compact models for the surface potential and surface longitudinal electric field based on the 2D solution of Poisson’s equation are introduced. The effects of the second gate on the threshold voltage roll-off are studied in this work. The introduced models are verified to have good agreement with the numerical simulation results. The results of the study show that the introduced structure with its newly introduced separately biased second gate provides some degree of freedom for controlling the ON-resistance and threshold voltage. A Verilog-A SPICE model for the drift region based on the introduced models is implemented to be compatible with circuit simulators along with standard MOSFET devices. Using this Verilog-A implementation, it is shown that the effective drift resistance is enhanced by approximately 14%, representing a 40% increase in the second gate bias at the same drift doping level. Moreover, increasing the drift doping slightly enhances the controllability of the effective drift resistance by 0.7%, representing a 40% increase in the second gate bias. By varying the second gate bias for the different drift region lengths from 1 to 2 μm, a 0.8% decrease in the controllability of the effective drift resistance versus the second gate bias is obtained. Also, the breakdown voltage is increased by about 6%, depending on drift doping level, as increasing the second gate voltage by about 40% from its nominal value.

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