Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources
Electronics & Communications Engineering Department
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FPGA has become a favorable platform for Systems-on-Chip (SoC). As SoC gets larger, a Network-on-Chip (NoC) emerges as a promising solution for communication problems among SoC's modules. Consequently, the importance of NoC on FPGAs has increased, not only to solve SoC's communication problems but also as a solution to FPGA's slow interconnects and to simplify Partial Dynamic Reconfiguration (PDR). Hard NoCs have better performance and consume less area and power than Soft NoCs. However, they are not configurable and they lead to a wasted area when the network is not in use. This makes the design of hard NoCs more critical to get an optimum performance while minimizing the wasted area as much as possible. In this paper, various NoC design parameters are evaluated to find the best-fit parameters that can be used in the non-configurable hard NoC design. In addition, different router architectures are investigated to select the optimum one for hard NoCs. Moreover, an efficient novel method for embedding the hard NoC inside the FPGA is proposed. The proposed NoC reduces the wasted area by using minimum and shareable resources. The NoC provides the FPGA with a high-performance communications infrastructure at a negligible cost. A total throughput of 0.33/1.3 Tbps (at a 32/128-bit flit width) is achieved on 65 nm technology at an added cost equivalent to the area of only 16/32 logic clusters.
(2018). Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources. Integration, 63, 138–147.
"Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources." Integration, vol. 63, 2018, pp. 138–147.