Dynamic and reliable multichannel interfacing system for FPGAs

Third Author's Department

Computer Science & Engineering Department

Fourth Author's Department

Computer Science & Engineering Department

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https://doi.org/10.1109/EUROCON52738.2021.9535622

Document Type

Research Article

Publication Title

EUROCON 2021 - 19th IEEE International Conference on Smart Technologies, Proceedings

Publication Date

7-6-2021

doi

10.1109/EUROCON52738.2021.9535622

Abstract

The focus in this paper is on FPGA-based systems with processors communicating with interchangeable device boards using shared interfaces implementing protocols such as UART, SPI, and I2C. A design is proposed to allow the dynamic interface switching using Dynamic Partial Reconfiguration (DPR) in order to increase performance or reliability during runtime. To this end, a reconfigurable interface block is introduced along with a switching block to connect any interface to different FPGA pins. Furthermore, it is shown how to add redundant interface blocks in order to achieve a pre-determined reliability level. Markov models are used in this analysis. All three protocols were implemented using DE10-Standard FPGA boards.

First Page

375

Last Page

380

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