Negative capacitance circuits for process variations compensation and timing yield improvement

Authors

Hassan Mostafa, Cairo University
Mohab Anis, American University in CairoFollow
Mohamed Elmasry, University of Waterloo

Files

Department

Electronics & Communications Engineering Department

Description

[abstract not available]

Publication Date

1-1-2014

Document Type

Book Chapter

Book Title

Canadian Conference on Electrical and Computer Engineering

ISBN

SCOPUS_ID:84908425613

Publisher

IEEE

City

Toronto, ON, Canada

First Page

1

Last Page

4

Keywords

deep sub-micron, Domino logic circuits, negative capacitance circuit, process variations, register file, Timing yield improvement

Recommended Citation

APA Citation

Mostafa, H. Anis, M. & Elmasry, M. (2014).Negative capacitance circuits for process variations compensation and timing yield improvement. IEEE. , 1-4
https://fount.aucegypt.edu/faculty_book_chapters/522

MLA Citation

Mostafa, Hassan, et al. Negative capacitance circuits for process variations compensation and timing yield improvement. IEEE, 2014.pp. 1-4
https://fount.aucegypt.edu/faculty_book_chapters/522