Negative capacitance circuits for process variations compensation and timing yield improvement

Chapter Title

Negative capacitance circuits for process variations compensation and timing yield improvement

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Department

Electronics & Communications Engineering Department

Description

[abstract not available]

Publication Date

1-1-2014

Document Type

Book Chapter

Book Title

Canadian Conference on Electrical and Computer Engineering

ISBN

SCOPUS_ID:84908425613

Publisher

IEEE

City

Toronto, ON, Canada

First Page

1

Last Page

4

Keywords

deep sub-micron, Domino logic circuits, negative capacitance circuit, process variations, register file, Timing yield improvement

Negative capacitance circuits for process variations compensation and timing yield improvement

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