Mitigation of Soft and Hard Errors in FPGA-Based Pacemakers

Authors

Gehad I. Alkady, American University in Cairo
Ihab Adly, Tegrom
Hassanein H. Amer, American University in CairoFollow
Tarek K. Refaat, Cisco Systems

Files

Department

Electronics & Communications Engineering Department

Description

[abstract not available]

Publication Date

2-11-2019

Document Type

Book Chapter

Book Title

Proceedings - 2018 13th International Conference on Computer Engineering and Systems, ICCES 2018

ISBN

9781538651117

Publisher

IEEE

City

Piscataway, NJ

First Page

284

Last Page

289

Keywords

Dynamic Partial Reconfiguration (DPR), fault tolerance, FPGA, markov model, pacemaker, reliability, sift-out, two DWC

Recommended Citation

APA Citation

Alkady, G. Adly, I. Amer, H. & Refaat, T. (2019).Mitigation of Soft and Hard Errors in FPGA-Based Pacemakers. IEEE. , 284-289
https://fount.aucegypt.edu/faculty_book_chapters/187

MLA Citation

Alkady, Gehad I., et al. Mitigation of Soft and Hard Errors in FPGA-Based Pacemakers. IEEE, 2019.pp. 284-289
https://fount.aucegypt.edu/faculty_book_chapters/187