One of the devices that play a great role in electronic circuits design, specifically safety-critical design applications, is Field programmable Gate Arrays (FPGAs). This is because of its high performance, re-configurability and low development cost. FPGAs are used in many applications such as data processing, networks, automotive, space and industrial applications. Negative impacts on the reliability of such applications result from moving to smaller feature sizes in the latest FPGA architectures. This increases the need for fault-tolerant techniques to improve reliability and extend system lifetime of FPGA-based applications. In this thesis, two fault-tolerant techniques for FPGA-based applications are proposed with a built-in fault detection region. A low cost fault detection scheme is proposed for detecting faults using the fault detection region used in both schemes. The fault detection scheme primarily detects open faults in the programmable interconnect resources in the FPGAs. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can be detected. For fault recovery, each scheme has its own fault recovery approach. The first approach uses a spare module and a 2-to-1 multiplexer to recover from any fault detected. On the other hand, the second approach recovers from any fault detected using the property of Partial Reconfiguration (PR) in the FPGAs. It relies on identifying a Partially Reconfigurable block (P_b) in the FPGA that is used in the recovery process after the first faulty module is identified in the system. This technique uses only one location to recover from faults in any of the FPGA’s modules and the FPGA interconnects. Simulation results show that both techniques can detect and recover from open faults. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can also be detected. Finally, both techniques require low area overhead.


Electronics & Communications Engineering Department

Degree Name

MS in Electronics & Communication Engineering

Graduation Date


Submission Date

June 2015

First Advisor

Amer, Hassanein Hamed

Committee Member 1

Abou Auf, Ahmed,RafikGuindy


122 p.

Document Type

Master's Thesis

Library of Congress Subject Heading 1

Field programmable gate arrays.

Library of Congress Subject Heading 2

Fault tolerance (Engineering)


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Institutional Review Board (IRB) Approval

Not necessary for this item


I would like to acknowledge both my supervisors: Prof. H.H. Amer and Dr. Mohamed Bakr for their great support throughout my thesis. I would also like to acknowledge Dr. Nahla Elaraby and Dr. Ahmed Madien for their assistance throughout my research. I would like to acknowledge my examiners Dr. Ahmed Abou Auf and Dr. Rafik El gendy for their valuable and constructive comments that help me a lot in improving the quality of this thesis. Finally, I would like to acknowledge the graduate program directors: Dr. Ayman El Ezabei and Dr Karim Seddik.