Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations.
Electronics & Communications Engineering Department
MS in Electronics & Communication Engineering
Online Submission Date
Anis, Mohab Hussein
Committee Member 1
Committee Member 2
Library of Congress Subject Heading 1
Integrated circuits -- Very large scale integration.
Library of Congress Subject Heading 2
Integrated circuits -- Design.
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(2014).Layout regularity metric as a fast indicator of process variations [Master’s thesis, the American University in Cairo]. AUC Knowledge Fountain.
Swillam, Esraa AbdelAzim AbdelHamid. Layout regularity metric as a fast indicator of process variations. 2014. American University in Cairo, Master's thesis. AUC Knowledge Fountain.